このサイトにおけるシノプシスの版権について

Synopsys, Design Compiler, Library Compiler, SmartModel, Memory Architect, BINMOS-CBA は日本国内における Synopsys, Inc. の登録商標です。

AMPS, Arcadia, CoCentric, COSSAP, Cyclone, DelayMill, DesignPower, DesignSource, DesignWare, Eagle Design Automation, EPIC, Formality, in-Sync, LEDA, ModelAccess, ModelTools, PathBlazer, PathMill, PowerArc, PowerMill, PrimeTime, RailMill, SmartLogic, SmartModel, SmartModels, SNUG, Solv-It, SolvNet, Stream Driven Simulator, Synopsys, TestBench Manager, TetraMAX, TimeMill, VERA は米国における Synopsys, Inc. の登録商標です。

BCView, Behavioral Compiler, BOA, BRT, Cedar, ClockTree Compiler, DC Expert, DC Expert Plus, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design Analyzer, Design Compiler, DesignSphere, DesignTime, Direct RTL, Direct Silicon Access, DW8051, DWPCI, ECL Compiler, ECO Compiler, ExpressModel, Floorplan Manager, FoundryModel, FPGA Compiler II, FPGA Express, Frame Compiler, HDL Advisor, HDL Compiler, Integrator, Interactive Waveform Viewer, Liberty, Library Compiler, ModelSource, Module Compiler, MS-3200, MS-3400, NanoSim, OpenVera, Physical Compiler, Power Compiler, PowerCODE, PowerGate, ProFPGA, Protocol Compiler, RoadRunner, Route Compiler, RTL Analyzer, Schematic Compiler, Scirocco, Shadow Debugger, SmartLicense, SmartModel Library, Source-Level Design, SWIFT, Synopsys Eaglei, Synopsys EagleV, SystemC, SystemC (logo), Test Compiler, TestGen, TimeTracker, Timing Annotator, Trace-On-Demand, VCS, VCS Express, VCSi, VHDL Compiler, VHDL System Simulator, VirSim, VMC, VSS は Synopsys,Inc. の商標です。

DesignSphere, TAP-in は、Synopsys,Inc. のサービスマークです。

DesignWare の商標使用権は日本シノプシスに帰属します。
Verilog は Cadence Design Systems 社の登録商標です。

その他、会社および商品名は各社の商標または登録名です。

(C) 日本シノプシス合同会社

お問合せ先：日本シノプシス合同会社 フィールド・マーケティング・グループ

最終更新日:2009年6月1日

Synopsys Server Copyright

Copyright (c)2001 Synopsys, Inc. All rights reserved.

Unless otherwise noted, any person is hereby authorized to view, copy, and print these documents subject to the following conditions:

  1. This document may be used for informational purposes only.
  2. Any copy of this document or portion thereof must include the copyright notice.
  3. This information is provided "AS IS" and without warranty of any kind, express, implied, statutory, or otherwise.

    Permission is not granted for resale or commercial distribution of the document, in whole or in part, or by itself or incorporated in another work.

Trademark Information

The following trademarks and service marks are the property of Synopsys, Inc.

Registered Marks:(R)
AMPS, Arcadia, CoCentric, COSSAP, Cyclone, DelayMill, DesignPower, DesignSource, DesignWare, Eagle Design Automation, EPIC, Formality, in-Sync, LEDA, ModelAccess, ModelTools, PathBlazer, PathMill, PowerArc, PowerMill, PrimeTime, RailMill, SmartLogic, SmartModel, SmartModels, SNUG, Solv-It, SolvNet, Stream Driven Simulator, Synopsys, TestBench Manager, TetraMAX, TimeMill, VERA

Trademarks: (TM)
BCView, Behavioral Compiler, BOA, BRT, Cedar, ClockTree Compiler, DC Expert, DC Expert Plus, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design Analyzer, Design Compiler, DesignSphere, DesignTime, Direct RTL, Direct Silicon Access, DW8051, DWPCI, ECL Compiler, ECO Compiler, ExpressModel, Floorplan Manager, FoundryModel, FPGA Compiler II, FPGA Express, Frame Compiler, HDL Advisor, HDL Compiler, Integrator, Interactive Waveform Viewer, Liberty, Library Compiler, ModelSource, Module Compiler, MS-3200, MS-3400, NanoSim, OpenVera, Physical Compiler, Power Compiler, PowerCODE, PowerGate, ProFPGA, Protocol Compiler, RoadRunner, Route Compiler, RTL Analyzer, Schematic Compiler, Scirocco, Shadow Debugger, SmartLicense, SmartModel Library, Source-Level Design, SWIFT, Synopsys Eaglei, Synopsys EagleV, SystemC, SystemC (logo), Test Compiler, TestGen, TimeTracker, Timing Annotator, Trace-On-Demand, VCS, VCS Express, VCSi, VHDL Compiler, VHDL System Simulator, VirSim, VMC, VSS

Service Marks: (SM)
DesignSphere, TAP-in

All other product or company names may be trademarks of their respective owners
Synopsys Copyright