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USB 2.0 Verification IP |
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Overview
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Synopsys Verification IP provides the building blocks neede by verification engineers to rapidly build environments that fully exercise the breadth of their SoC’s standard interfaces. The verification IP supports the features needed to support a constrained random verification methodology including messaging, notifications, scenario generators, callbacks, error injection and coverage.
Synopsys Verification IP supports Verilog testbenches on any simulator and SystemVerilog VMM testbenches on VCS. SystemVerilog UVM support is coming soon. Please click here for more information on UVM support.
Synopsys Verification IP is available in the VCS Verification Library or as single licenses.
- AMBA
| Verifies AMBA 2.0 and AMBA 3 AXI™ SoC designs | more |
| | Synopsys Verification IP for AMBA supports all data, address widths and transfer types. The AMBA 3 AXI Verification IP is AMBA 3 Assured. |
- PCI Express
| Verifies PCI Express endpoints, switch and root complex devices | more |
| | Synopsys Verification IP can be configured for verification at multiple levels including the 8b/10b and PIPE interfaces. It can verify both the MAC and PHY.  データシートのダウンロード |
- USB
| Verifies USB 1.1, 2.0, OTG, UTMI, UTMI+,ULPI, LPM, HSIC interfaces | more |
| | Synopsys Verification IP can be configured as a host or dual role device. The flexible programming with protocol checking verifies the USB host, hub or device データシートのダウンロード |
- USB 3.0
| Verifies USB Hosts, Devices and Hubs with support for SS, HS, FS | more |
| | Synopsys Verification IP for USB 3.0 is a multi-layered VIP for the verification of USB Hosts, Devices and Hubs with support for SuperSpeed, High Speed, Full Speed and Low Speed Interfaces. データシートのダウンロード |
- SATA
| Verifies SoC designs implementing the SATA interface | more |
| | Synopsys Verification IP provides device and monitor models to verify compliance of a SATA host interface with the SATA 2.5 specification. データシートのダウンロード |
| | The Synopsys Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to- PHY layer interfaces. データシートのダウンロード |
| | Synopsys Verification IP conforms to the RS-232 standards and supports, Serial I/O, General Purpose I/O and IrDA データシートのダウンロード |
- I2C
| Efficiently verifies the I2C bi-directional two-wire bus | more |
| | The Synopsys I2C Verification IP is compliant with version 2.1 of the Philips I2C-Bus specification and supports standard, fast and high speed operations. データシートのダウンロード |
- PCI/PCI-X
| Verifies proper operation of the PCI and PCI-X specifications | more |
| | Synopsys Verification IP helps to create a virtual PCI or PCI-X system around the design, enabling quick and efficient generation of tests. データシートのダウンロード |
- OCP
| Functionally verifies OCP 2.0/2.1/2.2 and 3.0 Interfaces | more |
| | Synopsys Verification IP verifies the master and slave devices in OCP systems and provides 100% functional coverage of the OCP-IP 2.0/2.1/2.2 and 3.0 compliance checks データシートのダウンロード |
| | Synopsys provides over 10,000 memory models, supporting over 25 memory vendors. The memory models help ensure model accuracy, quality and reliability. データシートのダウンロード |
- Star IP
| Design Views of High Value Star IP from IBM, NXP and Altera | more |
| IBM PowerPC | Includes simulation and timing models, verification environment and full documentation for the synthesizable PowerPC
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| | The VCS Verification Library gives engineers access to all Synopsys Verification IP such as PCI Express, USB and AMBA, in a single license. データシートのダウンロード |
| | Portfolio of tool-independent SystemC compliant transaction-level models which serve as the building blocks of virtual platforms. |
| | NoBug's DDR3 SDRAM is a high-speed CMOS, dynamic random-access memory |
| | DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory |
- MIPI HSI
| VMM-enabled MIPI HSI Verification IP (Alliance VIP) | more |
| | eInfoChip’s MIPI HSI VIP is compliant with the latest MIPI HSI physical layer specification Version 1.01.00 |
Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
The Verification Methodology Manual for SystemVerilog, co-authored by Synopsys and ARM, defines a coverage-driven, constrained random methodology that speeds time to reach coverage goals. DesignWare Verification IP provides extensive support for the VMM and includes scenario generators and transactors to significantly reduce testbench development time.
Verification IP and Native Testbench
For high performance verification, DesignWare Verification IP supports VCS Native Testbench (NTB) technology. VCS compiles the Verification IP natively to provide up to five times faster runtime performance. DesignWare Verification IP also supports Pioneer NTB, Synopsys testbench automation tool, to give high performance in ModelSim and NC-Sim simulation environments.
VCS Verification Library
The VCS Verification includes all of the DesignWare standards-based verification IP and Star IP design views. The broad portfolio of the verification IP in the VCS Verification Library integrates easily into SystemVerilog, Verilog, OpenVera and VHDL testbenches to generate and respond to bus traffic, check for protocol violations, and generate coverage reports. The VCS Verification Library supports the Verification Methodology Manual (VMM) for SystemVerilog using Synopsys' Reference Verification Methodology (RVM).
- Key Benefits
Broadest verification IP portfolio in the industry
Delivers 5X simulation performance improvement with VCS
Supports proven verification methodology for SystemVerilog
Includes example testbenches to accelerate learning and speed testbench development
The DesignWare Verification IP Alliance program gives designers access to a broader range of VMM-enabled verification IP, which complements DesignWare Verification IP. Members of the Alliance program have been pre-qualified by Synopsys for their extensive experience in verification methodology, VMM and verification IP development. The Verification IP included in the Alliance program is available from the member companies. It is developed using the same guidelines as the DesignWare Verification IP to help ensure that a consistent use model is delivered to designers.
The current Alliance members include:
eInfochips Inc. is a provider of product development solutions and services to Semiconductor companies worldwide. eInfochips’ goal is to help companies address their challenges related to IP integration, verification and technology migration in order to reduce the time to market for their products. eInfochips expertise spans design, verification, HVL-based verification methodology, system validation, and industry standard Verification IP development.
NoBug is an expert digital design verification company that masters a full range of technologies (functional, formal and assertion-based) with a variety of tools and languages (SystemVerilog,RuleBase, Vera, Verilog-PLI/C). NoBug’s goal is to establish strategic customer/client relationships designed to help deliver a customer-centric, total solutions approach to solving problems, developing business opportunities and creating sustainable advantage for their customers.
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