| Janick Bergeron is a Scientist at Synopsys,
Inc. He is the author of the best-selling book Writing Testbenches:
Functional Verification of HDL Models and the moderator of the
Verification Guild. He holds a Masters degree in Electrical Engineering
from the University of Waterloo, a Bachelor of Engineering from
the Universite du Quebec a Chicoutimi, and a MBA degree from
the University of Oregon.
Eduard Cerny, Ph.D. (McGill University), is a Principal Engineer,
R&D, in the Verification Group at Synopsys, Inc. He joined
Synopsys in 2001 after 25 years in academia, as Professor of
Computer Science at the Universite de Montreal. His interests
have been in design, verification and test of hardware, and
he is author of many articles in these areas.
Alan Hunter, BEng(Hons), MSc, is the Design Verification Methodology
Programme manager at ARM Ltd and leads the design verification
methodology work for ARM worldwide. This work covers all areas
from CPU design verification through systems and system component
design verification. His main areas of interest include optimizing
design verification efficiency and quality, formal methods,
and determinism in the design verification flow.
Andrew Nightingale, BEng(Hons), MBCS CITP,
is a consultant engineer at ARM Ltd and has led the SoC Verification
group in
ARM's Cambridge and Sheffield design centers for several years.
The group covers ARM PrimeXsysTM platforms and Prime-Cell
development, including advanced AXI- and AHB-based system backplane
components
such as bus interconnects and high-performance memory controllers.
PrimeXsys is a trademark of ARM Limited. |
